Control signals are often implemented using pulse width modulation. The width of the pulse is usually an integer multiple of the period of a clock cycle in the domain in which the control signal was manifested. These control signals are most easily transferred between circuits using pre-existing busses. However, if the clock frequency of a bus is not some integer multiple of the circuit in which the control signal was originated, maintaining the same pulse width is a problem. Conventional approaches synchronize signals using two back to back registers. However, the pulse width of the control signal is not maintained.
It would be desirable to transfer a control signal pulse of variable pulse width from one clock domain to another with minimum latency while maintaining the pulse width in terms of number of clocks in the first clock domain.